Cryptography
AES硬件架构
AES hardware architecturesHardware implementations of the Advanced Encryption Standard (AES) algorithm designed for high performance and low power consumption in integrated circuits. / 高性能、低功耗的AES算法集成电路硬件实现。
- Knowledge type
- 物理设备
- First proposed or discovered
- Proposer
- Turkey Farm member
- Creator
- 农场主
- Last updated
- 2026-10-31 19:06:33
Sub-knowledge points
Rijndael extensionsnon-standard Rijndael extensions
Higher-order knowledge points
No connected node yet
Main parameters and performance indicators
key length: up to 1024 bitstechnology: FPGA and 45-nm ASIC
Open problems
No unresolved problem recorded yet
Related literature
ranked by community starsAES hardware architectures and non-standard Rijndael extensions up to 1024-bit keys: An open-source FPGA and 45-nm ASIC evaluationOpen source
Related products and links
FPGA implementation45-nm ASIC implementation
Creation and modification trail
1 recordsRecord title: AES hardware architectures.
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