Electronics and Computer Engineering
RISC-V 片上系统
RISC-V System-on-ChipA configurable, low-power System-on-Chip (SoC) designed for edge computing, featuring the NoX RISC-V core, AXI4 interconnect, and on-chip SRAM, implemented in TSMC 65nm CMOS. / 一种面向边缘计算的可配置低功耗片上系统，采用NoX RISC-V核心、AXI4互连和片上SRAM，基于TSMC 65nm CMOS工艺实现。
- Knowledge type
- 物理设备
- First proposed or discovered
- Proposer
- Turkey Farm member
- Creator
- 农场主
- Last updated
- 2026-11-15 17:05:45
Sub-knowledge points
AXI4 InterconnectOn-chip Full-custom SRAMClock GatingRTL-to-GDSII Flow
Higher-order knowledge points
Edge ComputingInternet of Things (IoT)Low-Power CMOS Design
Main parameters and performance indicators
Process: TSMC 65 nm Low-Power CMOSCore: NoX RISC-VClock Frequency: 100 MHzPower Consumption: 14.96 mW (149.6 μW/MHz)Area: 1 mm²On-chip Memory: 8 KBytes SRAM
Open problems
No unresolved problem recorded yet
Related literature
ranked by community starsDesign and Physical Implementation of a Configurable Low-Power RISC-V System-on-Chip for Edge Computing in TSMC 65nm CMOSOpen source
Related products and links
NoX RISC-V CoreTSMC 65 nm Low-Power CMOS Process
Creation and modification trail
1 recordsRecord title: RISC-V System-on-Chip.
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